This invention relates to clock data recovery (CDR) technology, and more particularly to CDR circuitry that accommodates a wider range of frequency and run-length requirements.
An increasingly important type of signaling between devices is signaling in which the clock signal information is embedded in a serial data stream so that no separate clock signal needs to be transmitted. The clock signal is “recovered” at the receiver and used in processing the data stream. This general type of signaling is commonly referred to as “clock data recovery” or “CDR” signaling. U.S. patent application Ser. No. 09/805,843, filed on Mar. 13, 2001, and Ser. No. 10/454,731, filed on Jun. 3, 2003, describe various aspects of CDR signaling and are hereby incorporated herein by reference in their entirety.
In one type of CDR signaling, the frequency of the clock signal is known by the receiver, and the phase information for the clock signal is recovered from the data signal by the high-to-low and/or low-to-high transitions in the data signal. An oscillator at the receiver provides a clock signal having the known frequency, and phase information embedded in the data signal is used to adjust the phase of the receiver clock signal.
Clock data recovery can be accomplished in many ways to meet the demands of particular applications. However, a CDR implementation for one application may not meet the demands of another application having different criteria. The trend in technology is towards the convergence of many different applications into a single device, and it would be desirable to employ CDR circuitry that can accommodate those many different applications. Furthermore, the fast pace of improvements in technology for the same application demands that CDR circuitry be robust enough to operate in modern applications and yet be flexible enough to accommodate future improvements as well. Accordingly, there is continued interest in improving CDR technology.